Delay Analysis of VLSI Interconnections Using the Di usion Equation Model

The traditional analysis of signal delay in a transmission line begins with a lossless LC representation, which yields a wave equation governing the system response; 2-port parameters are typically derived and the solution is obtained in the transform domain. In this paper, we begin with a distributed RC line model of the interconnect and analytically solve the resulting di usion equation for the voltage response. A new closed form expression for voltage response is obtained by incorporating appropriate boundary conditions for interconnect delay analysis. Calculations of 50% and 90% delay times for various cases of interest (e.g., open-ended RC line) give substantially di erent estimates from those commonly cited in the literature, thus suggesting revised delay estimation methodologies and intuitions for the design of VLSI interconnects. The discussion furthermore provides a unifying treatment of the past three decades of RC interconnect delay analyses. 1 Overview Delay analysis of VLSI interconnections is a key element in timing veri cation, gate-level simulation and performance-driven layout design. The standard approach to modeling interconnect delay has been based on a simple lossless LC model which considers only inductances (L) and capacitances (C). For this lossless model, the relationship between v and i gives rise to a second-order partial di erential equation of the form [9]: @v @x2 = LC @ v @t2 (1) and the solution to this wave equation is of the form v(x) = A1e x + A2e x (2) This work was supportedby NSF Young InvestigatorAward MIP-9257982. Part of the work of S. Muddu was done during the course of a Summer 1993 internship at Intel Corporation. where propagation constant |! p lc (l and c are the inductance and capacitance per unit length, and ! is the wave frequency). One easily extends this model to lossy (RLC) interconnects by incorporating a series resistance. The same equations obtained for the lossless model can be used, with ZL = R + |!L = |![ R |! + L]; i.e., ZL = |!L0 where L0 = R |! + L is the new inductance value. Similarly, one may incorporate a conductance G via ZC = G + |!C = |![ G |! + C]; i.e., ZC = |!C0 where C0 = G |! +C is the new capacitance. The same solution derived for the lossless model can incorporate the new L0 and C0 values to capture the attenuation factor in lossy lines. Using the solution (2) to the wave equation, and the characteristic impedance of the line, one may treat the interconnect line as a 2-port and obtain equations for voltage and current at the terminal side of the 2port in terms of voltage and current at the source side. This yields the 2-port matrix parameters, e.g., ABCD parameters. To obtain the transient time-domain response of an interconnect line, the standard approach has been to calculate the response in the transform domain using 2-port parameters, and then apply inverse transforms to obtain the response in the time domain. We call this the LC analysis, or wave equation, approach. Since it may be complicated to apply the inverse transforms, various approximations are typically made which simplify the resulting expressions for the time-domain response. For the well-studied case of an RC transmission line, the traditional LC analysis is extended to an RLC analysis after which L is set to zero. But by contrast, if we initially model the interconnect as a pure distributed RC line, we obtain a di usion equation (or heat equation) from which the solution for the transient response, depending on boundary conditions, can be calculated analytically. This RC-based delay analysis approach, and its implications, are the subject of the present paper. Our motivation for adopting the RC-based delay analysis is as follows. For previous generation interconnects, such as for PCB, the resistance per unit length (r) is considerably smaller than the inductive impedance (!l), i.e., r !l, so that the conventional LC-based analysis seems reasonable. However, with small feature sizes of thinlm and IC interconnects, we now nd that r !l up to frequencies of O(1) GHz, and even at frequencies above O(1) GHz, both terms are of comparable magnitude [13]. Thus, in the present regime of highly resistive interconnects, it seems natural to begin with an RC, rather than LC, model in obtaining the delay estimate. While the RC-based perspective and the resulting di usion equation have been noted by many authors, no closed form expression for the voltage response has been derived using appropriate boundary conditions. Indeed, this is a central contribution of our work. Our analysis based on the di usion equation yields a simple analytical expression for the voltage response. Furthermore, though the solution of the di usion equation does not refer directly to any wave propagation mechanism, we may yet consider re ections at discontinuities through the analogy of voltage propagation by electromagnetic vibrations (waves) to the propagation of heat waves [5]. To achieve a comparison with previous works, we study the case of an open-ended RC line with ideal source, as well as other idealized cases which have been treated in the literature. Delay estimates calculated from our di usion equation analysis are substantially di erent from previous delay estimates, and we believe that this discrepancy may prove signi cant for future e orts in interconnect modeling and design. We furthermore extend our delay analysis to the case of arbitrary source and load impedances by considering re ections at the source and load. Finally, our analysis a ord delay calculations at arbitrary locations on the distributed RC line. 2 Previous Delay-Time Approximations for an RC Line 2.1 Lumped Models Approximating the interconnect resistance and capacitance by lumped values R and C gives the timedomain response v(t) = V0(1 e t RC ) where V0 is the input voltage applied. With this model, the delay to reach the 63% voltage threshold is 1:0RC.